Field of the Invention
The invention relates to an array sensor, and more particularly to a memory architecture of an array sensor.
Description of the Related Art
In recent years, biological identification technology has become increasingly mature, and different biological features can be used for identifying users. Since the recognition rate and accuracy of fingerprint identification technology are better than those of other biological feature identification technologies, fingerprint identification and verification is used extensively in various areas.
Fingerprint identification and verification technology detects a user's fingerprint pattern by using an array sensor, captures specific fingerprint data from the fingerprint pattern and saves the fingerprint data into the memory or directly stores the fingerprint pattern. Thereafter, when the user presses or swipes a finger on or over the fingerprint sensor again, the fingerprint sensor senses the fingerprint pattern and captures fingerprint data, so as to compare with the previously stored fingerprint data, or directly compares with the previously stored fingerprint pattern for identification. If the two match, then the user's identity is confirmed.
FIG. 1 shows a layout schematic illustrating a conventional sensing chip 10 disposed in an array sensor. The sensing chip 10 comprises a digital circuit 11, a sensing array 12, an analog circuit 13 and a plurality of memories, wherein the memories comprise the static random access memories (SRAMs) 14A-14F and the read only memories (ROMs) 16A-16B. In FIG. 1, the SRAMs 14A-14F and the ROMs 16A-16B are disposed around the sensing array 12. Therefore, when the amount of the memories that the sensing chip 10 needs to perform operations increases, the layout area of the sensing chip 10 is increased. Furthermore, for the related signals and the logic units in the digital circuit 11 capable of accessing various regions of the memories, setup/hold time violations will easily occur in the layout, thereby increasing the difficulty of the layout. In design processes of an integrated circuit, additional time and efforts are needed to solve these time violations.